Advanced Synthesis & STA/Constraints

• Usage of CCD ( concurrent clock Data) optimisation in synthesis
• Understanding silicon Freq and STA freq
• Understanding Do-use and Dont Use
• Fusion Compiler based one-graph synthesis and PnR
• Making Floorplan changes in Physical Aware synthesis
• Analysing and Debugging Elaborate stage of synthesis
• What if analysis of timing and bottleneck
• STA analysis for MVMS( Multiple Voltage Multiple Supply) Designs