• Introduction to Design for Test (DFT)
• Overview of SOC flow for DFT
• Digital Circuits related to DFT
• Sample Verilog Syntax
• Duration: 1 Week

• IEEE 1149.1 JTAG Architecture and Operation
• TAP Controller and FSM
• JTAG and Boundary Scan
• BSR Cell Types and Usage
• IEEE 1687 iJTAG Architecture
• ICL, PDL Overview


• Labs
• Duration: 2 Weeks

• SCAN Architecture Overview
• Types of SCAN cells
• Scan Chains Operation
• Various DFT Blocks (for SCAN)
• Duration: 1 Week

• Block level SCAN Insertion Flow (Without Compression)
• Multiple Clock Handling
• Analysis of various SCAN DRC's
• DRC Fixes with Examples
• How to handle Pre-existing chain (like CTL)
• Labs
• Duration: 2 Weeks

• Needs of Compression Logic
• Compression Architecture
• Different Compression Techniques
• SCAN Stitching with Compression
• Block level SCAN Insertion Flow (with Compression)
• Different types of Mask techniques
• LEC Checks (Pre vs Post Scan Insertion)
• Labs
• Duration: 2 Weeks

• Introduction to ATPG
• Understanding of Defects and Faults
• Types of Fault models
• Block level ATPG Flow (Stuck-At)
• ATPG constraints and Analysis
• ATPG DRC analysis (C, D, K, and T rules)


• Test Coverage Analysis


• Coverage Improvement Techniques


• Labs
• Duration: 2 Weeks

• Different Types of At-Speed Fault Models
• At-Speed fault model (In Details)
• Concept of LOC, LOS and LEOS
• On-Chip clocking for At-Speed Testing
• ATPG TDF Setup and Pattern Generation
• Analysing Low TDF coverage and Improvement
• ATPG TDF Setup and Pattern Generation
• Introduction to Test Point Insertion
• Labs
• Duration: 2 Weeks

• Introduction to Static Timing Analysis
• Different Timing Corners
• Timing Constraints (Test Modes)
• Sample SDC file (Test Modes)
• Duration: 1 Week

• Simulation Overview (Zero-delay, Unit-delay)
• Different between Parallel and Serial simulations
• Pattern Simulation and Debug (Chain, Logic, Parallel, Serial)
• Timing Simulations with SDF
• Labs
• Duration: 1 Week

• Introduction to MBIST
• MBIST Architecture Overview and Memory Grouping
• Memory Fault types and Memory Testing Algorithms
• MBIST Insertion Flow (Bottom-Up)
• MBIST Pattern Generation Flow
• MBIST Pattern Verification
• Labs
• Duration: 2 Weeks

Introduction to HDL

• History of HDL


• Need and Scope Of HDL

Basic Concepts

• Types of Modeling


• Data Types in Verilog, System Task


• Logic Values


• Port Definition, Declaration


• Port Connection Rule

Gate Level Modeling

• Gate Types


• Gate Delays


• Vectors in Verilog


• Test Bench Basics


• Writing Verilog Modules


• Gate Level Modeling Examples

Dataflow Modeling

• Type of Operators


• Continuous assignment statement


• Regular assignment delay


• Examples Of Data Flow Modeling

Behavioral Modeling

• Initial and Always Statements


• Procedural Assignment Statements


• Timing Control Statements


• If_ else Statements


• Case statement


• Block Statements


• Loops


• Design of Flip-flops


• Design of Digital circuits using Behavioral Modeling

Tasks and Functions

State Machines

• Moore Machines


• Mealy Machines


• Examples of Moore and Mealy Machines

System Verilog Overview

• Overview of SystemVerilog


• SystemVerilog Books and Resources

Data Types

• System verilog data types and enumerated types


• Operators


• Queues and Arrays


• Typedefs


• Structures and unions


• Casting


• Packages


• Strings

Flow Control

• Loop enhancements


• Tasks and Functions


• Time values

OOP in System Verilog

• Basics of OOP


• Class Based Randomization


• Advanced OOP


• Class extension & inheritance


• Adding properties & methods to extended classes


• Overriding class methods


• Extending class methods


• Virtual Classes, Methods and Polymorphism


• Dynamic Casting and Parameterized Classes


• Callbacks

Advanced Concepts

• Event scheduling in Verilog 2001


• Event scheduling in System Verilog

Interfaces

• Interface usage overview


• How interfaces work


• Interface constructs


• Interface mod ports

Process Synchronization

• Fork-join processes


• Semaphores


• Events


• Mailboxes

Program Blocks

• Program blocks


• Program block interaction with modules


• Final blocks


• Clocking blocks


• Clocking skews

Functional Coverage

• Types of coverage
• Functional coverage process
• Cover groups and cover points
• Coverage bins
• Cross coverage

System Verilog Assertions

• Assertion based verification


• Assertion types


• Operators


• Property


• Sequence


• Operations


• Binding SVA to Design Blocks


• Assertion directives