JTAG and Scan Insertion

WEEK -1

• Full ASIC flow – DFT
• DFT Basics
• Boundary scan / JTAG basics
• Boundary scan cell operation in detail
• JTAG operation
• TAP controller state machine

WEEK -2

• Understanding of SCAN in depth
• Types of Scan architecture
• Scan architecture overview

WEEK -3

• Test cases assignments review
• Assessment on Boundary scan

WEEK -4

• Scan design rules
• Design Rule Checking (DRC)
• DRC Fixing with examples

WEEK -5

• Full scan insertion and stitching without compression
• Multiple clock domains in SoC
• Handling multiple clock domains during shift and capture

WEEK -6

• Basics and Need of Compression
• Compression techniques
• Scan insertion with compression
• On-chip clocking for at-speed testing
• Hierarchical Scan Design

WEEK -7

• Test cases assignments review
• Assessment on Scan Insertion

ATPG and Simulations

WEEK -1

• DFT Overview – ATPG
• Understanding of Defects and Faults
• Types of fault models
• Basic concepts of ATPG
• ATPG algorithm
• Different types of ATPG

WEEK -2

• Stuck-at fault model (In detail)
• Understanding of ATPG constraints
• ATPG DRC analysis
• ATPG for Stuck-at fault model
• Coverage improvement techniques

WEEK -3

• At speed fault model (In detail)
• Understanding Transition fault ATPG
• ATPG setup for transition fault model
• ATPG for Transition fault model

WEEK -4

• Introduction to Diagnosis
• Diagnosis Flow
• Analyzing failure logs
• Chain Failure Diagnosis
• Successful results

WEEK -5

• Test cases assignments review
• Assessment on ATPG & Simulations

WEEK -6

• Preparation for Interviews & guidance

Introduction to HDL

• History of HDL


• Need and Scope Of HDL

Basic Concepts

• Types of Modeling


• Data Types in Verilog, System Task


• Logic Values


• Port Definition, Declaration


• Port Connection Rule

Gate Level Modeling

• Gate Types


• Gate Delays


• Vectors in Verilog


• Test Bench Basics


• Writing Verilog Modules


• Gate Level Modeling Examples

Dataflow Modeling

• Type of Operators


• Continuous assignment statement


• Regular assignment delay


• Examples Of Data Flow Modeling

Behavioral Modeling

• Initial and Always Statements


• Procedural Assignment Statements


• Timing Control Statements


• If_ else Statements


• Case statement


• Block Statements


• Loops


• Design of Flip-flops


• Design of Digital circuits using Behavioral Modeling

Tasks and Functions

State Machines

• Moore Machines


• Mealy Machines


• Examples of Moore and Mealy Machines

System Verilog Overview

• Overview of SystemVerilog


• SystemVerilog Books and Resources

Data Types

• System verilog data types and enumerated types


• Operators


• Queues and Arrays


• Typedefs


• Structures and unions


• Casting


• Packages


• Strings

Flow Control

• Loop enhancements


• Tasks and Functions


• Time values

OOP in System Verilog

• Basics of OOP


• Class Based Randomization


• Advanced OOP


• Class extension & inheritance


• Adding properties & methods to extended classes


• Overriding class methods


• Extending class methods


• Virtual Classes, Methods and Polymorphism


• Dynamic Casting and Parameterized Classes


• Callbacks

Advanced Concepts

• Event scheduling in Verilog 2001


• Event scheduling in System Verilog

Interfaces

• Interface usage overview


• How interfaces work


• Interface constructs


• Interface mod ports

Process Synchronization

• Fork-join processes


• Semaphores


• Events


• Mailboxes

Program Blocks

• Program blocks


• Program block interaction with modules


• Final blocks


• Clocking blocks


• Clocking skews

Functional Coverage

• Types of coverage
• Functional coverage process
• Cover groups and cover points
• Coverage bins
• Cross coverage

System Verilog Assertions

• Assertion based verification


• Assertion types


• Operators


• Property


• Sequence


• Operations


• Binding SVA to Design Blocks


• Assertion directives