Course Highlights :-
- 1 Dedicated Mentor
- Support24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation
Eligibility Criteria :-
- B.E/B.Tech in ECE/EEE.
- M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
- 60% through out Academics
Course Duration :-
- Introduction to Physical Design
- Introduction to Synthesis
- Introduction to Floorplan
- Introduction to Placement
- Introduction to Clock -Tree-Synthesis
- Introduction to DFM
- Sythesis & pre-layout STA
- Floorplan
- Placement
- Routing
- DFM(Design for manufacturing) & PV
- Post -layout STA
Introduction to HDL
- History of HDL
- Need and Scope Of HDL
Basic Concepts
- Types of Modeling
- Data Types in Verilog, System Task
- Logic Values
- Port Definition, Declaration
- Port Connection Rule
Gate Level Modeling
- Gate Types
- Gate Delays
- Vectors in Verilog
- Test Bench Basics
- Writing Verilog Modules
- Gate Level Modeling Examples
Dataflow Modeling
- Type of Operators
- Continuous assignment statement
- Regular assignment delay
- Examples Of Data Flow Modeling
Behavioral Modeling
- Initial and Always Statements
- Procedural Assignment Statements
- Timing Control Statements
- If_ else Statements
- Case statement
- Block Statements
- Loops
- Design of Flip-flops
- Design of Digital circuits using Behavioral Modeling
Tasks and Functions
State Machines
- Moore Machines
- Mealy Machines
- Examples of Moore and Mealy Machines
System Verilog Overview
- Overview of SystemVerilog
- SystemVerilog Books and Resources
Data Types
- System verilog data types and enumerated types
- Operators
- Queues and Arrays
- Typedefs
- Structures and unions
- Casting
- Packages
- Strings
Flow Control
- Loop enhancements
- Tasks and Functions
- Time values
OOP in System Verilog
- Basics of OOP
- Class Based Randomization
- Advanced OOP
- Class extension & inheritance
- Adding properties & methods to extended classes
- Overriding class methods
- Extending class methods
- Virtual Classes, Methods and Polymorphism
- Dynamic Casting and Parameterized Classes
- Callbacks
Advanced Concepts
- Event scheduling in Verilog 2001
- Event scheduling in System Verilog
Interfaces
- Interface usage overview
- How interfaces work
- Interface constructs
- Interface mod ports
Process Synchronization
- Fork-join processes
- Semaphores
- Events
- Mailboxes
Program Blocks
- Program blocks
- Program block interaction with modules
- Final blocks
- Clocking blocks
- Clocking skews
Functional Coverage
- Types of coverage
- Functional coverage process
- Cover groups and cover points
- Coverage bins
- Cross coverage
System Verilog Assertions
- Assertion based verification
- Assertion types
- Operators
- Property
- Sequence
- Operations
- Binding SVA to Design Blocks
- Assertion directives
