Scrolling text Physical design : Hyderabad (Offline/Online) : classes will start on 23rd January 2025    ||   Design for Testability (DFT) : Bangalore (Offline/Online) : classes will start on 20th January 2025


Analog Layout Course

Course Highlights :-

  • More than 1000+ Mock interview questions and answers to equip students for cracking any job interviews , along with Cover-letter and Resume preparation , Soft-Skills Development.
  • 18+yrs Instructor Team Led Training. Flexible training to meet your needs. Semicon courses are delivered by subject matter experts and can be delivered via classroom or virtual (live on-line).
  • Self Paced Learning. Semicon offers rich self-paced training content to accelerate your learning "when you need, wherever you need". The online courses are accessible 24x7 and are organized in a way that allows you to consume the content at your own pace.
  • Synopsys or Cadence EDA Tools set for mastering tools and be Industry ready to jump-start career in VLSI.
  • Weekly Assignment Tests and 1:1s to track and make suitable adjustments to the progress of learning and mastering Analog Layout in VLSI.
  • 1 year online technical ramp-up support and Semicon technical materials access after course completion.
  • Every week-end Sunday free youtube live session on Technical topics presentations.

Eligibility Criteria :-

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
  • 60% through out Academics

Course Duration :-

  • 3-4 Months

EDA Tools :-

    Tools : (Synopsys Tools or Cadence Tools)
  • Custom Compiler or Virtuoso ( For Analog/AMS/Std-cells/IO/Memory/Custom Layout )
  • ICV ( For Physical Verification (DRC/LVS/ANT) )

    • Working Hours :-

    • Monday to Friday (9AM to 6:30PM) and Saturday (10AM to 1PM)
      • Note:-
    • Institute will remain closed on sundays and all public holidays.

Syllabus : ( Analog Layout - Mentorship )

  • Module 1: VLSI ( Very Large Scale Integration ) , Semiconductors , Transistors
  • Module 2: History of VLSI ( SSI/MSI/LSI )
  • Module 3: ASIC/SoC/FPGA , PPA ( Power Performance Area )
  • Module 4: Moore's Law
  • Duration: Week 1

  • Module 5: Combination Circuits ( AND/OR/NAND/NOR etc )
  • Module 6: Sequential Circuits ( Flip-Flops/Latches/Memorys etc )
  • Duration: Week 2

  • Module 7: CMOS ( Complimentary Metal Oxide Semiconductor )
  • Module 8: FinFet ( Field Effect Transistors ) , Double-Patterning
  • Module 9: Technology Nodes ( 3nm/5nm/7nm/10nm/12nm/16nm etc )
  • Module 10: Fabrication Process ( Oxidation/Deposition/Lithography/ Etching/Diffusion/Ion Implantation )
  • Duration: Week 3

  • Module 11: Full-Custom Cycle Flow Chart
  • Module 12: Front-End and Back-End
  • Module 13: Fab and Packaging
  • Duration: Week 4

  • Module 14: PN Junction Diode, BJT/FET/NMOS/CMOS/FINFET
  • Duration: Week 5

  • Module 15: Understanding schematic symbols and parameters
  • Module 16: Creating and managing libraries and cells
  • Module 17: CMOS and BI-CMOS layout techniques
  • Module 18: Resistor and Capacitor Techniques
  • Duration: Week 6-9

  • Module 19: Inverter, AND, OR, NAND, NOR, Latches and Flops
  • Duration: Week 10

  • Module 20: IO Layout Guidelines,SRAM/DRAM/ROM Memory Layout
  • Duration: Week 10

  • Module 21: PLL, DLL, ADC's, DAC,s etc including current minor layout, well proximity effect
  • Duration: Week 10

    - Physical Verification (DRC/LVS/ANT).
  • Module 22: Physical Verification DRC ( Design Rule Check )
  • Module 23: Physical Verification LVS ( Layout Versus Schematic )
  • Module 24: Physical Verification ANT (Antenna)
    • - EMIR.
  • Module 25: Static EMIR
  • Module 26: Dynamic EMIR
  • Duration: Week 11

  • Module 27: TCL Scripting
  • Module 28: Perl Scripting
  • Module 29: Python Scripting
  • Module 30: Shell Scripting
  • Module 31: Unix and GVIM
  • Duration: Week 11

  • Module 32: Mock Interviews
  • Module 33: Cover-letter and Resume Preparation
  • Module 34: Interview Guidance
  • Module 35: Soft-Skills Training
  • Duration: Week 12

  • Module 36: Project using Synopsys Tools or Project using Cadence Tools
  • Module 37: Flow Automation
  • Module 38: AI and ML
  • Module 39: Run Time Reduction

  • Module 40: Integration Guidelines , Seal Ring , Scribe Line etc
  • Duration: Week 12
The Analog Layout Course content is designed to cover Layout wrt CMOS and FinFet; and 2 different Sign-off checks. This will extensively help to open-up wide VLSI job opportunities for students as their domains expertize will be vast.


At the end of the Analog Layout Course:
  • Be experienced to handle Layouts for any Schematic Designs.
  • Gain Hands-On experience in using EDA Tools.
  • Have through understanding of full ASIC/SoC Implementation flow steps.
    • Geared-up in below different Domains :
    • - Analog Layout (AL) Deep-Dive for handling Chip and Blocks.
    • - AMS , Custom , IO , Std-cells , Memory Layouts.
    • - Sign-off checks wrt :
    • - Physical Verification (DRC/LVS/ANT)
    • - EMIR
  • Flow automation using Scripting : Tcl/Perl/Python/Shell/Unix and GVIM.
  • Equipped with 1000+ Mock Interview Questions and Answers ,Cover-letter and Resume, Soft-Skills.