Course Highlights :-
- 1-1 Dedicated Mentor.
- Support 24/7 Tool Access.
- Multiple MOCK Interviews.
- Industry Standard Projects.
- Resume Preparation.
Eligibility Criteria :-
- B.E/B.Tech in ECE/EEE.
- M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
- 60% through out Academics
Course Duration :-
Introduction to VLSI
- Application of VLSI
- Design Process of VLSI
- Scope of VLSI
- Introduction to VLSI Design flow
Digital System Design
- Number Systems - Review
- Logic Minimization
- Combinational Circuit Design
- Understanding of a Logic Gate
- Designing with Mux, Demux, Decoders, Encoders
- Sequential Elements - D Latch, D Flop
- Design of Sequential Systems - Registers and Counters
- Finite State Machine
Introduction to HDL
- History of HDL
- Need and Scope Of HDL
Basic Concepts
- Types of Modeling
- Data Types in Verilog, System Task
- Logic Values
- Port Definition, Declaration
- Port Connection Rule
Gate Level Modeling
- Gate Types
- Gate Delays
- Vectors in Verilog
- Test Bench Basics
- Writing Verilog Modules
- Gate Level Modeling Examples
Dataflow Modeling
- Type of Operators
- Continuous assignment statement
- Regular assignment delay
- Examples Of Data Flow Modeling
Behavioral Modeling
- Initial and Always Statements
- Procedural Assignment Statements
- Timing Control Statements
- If_ else Statements
- Case statement
- Block Statements
- Loops
- Design of Flip-flops
- Design of Digital circuits using Behavioral Modeling
Tasks and Functions
State Machines
- Moore Machines
- Mealy Machines
- Examples of Moore and Mealy Machines
