ASIC Verification

Course Highlights :-

  • More than 500+ Mock interview questions and answers to equip students for cracking any job interviews , along with Cover-letter and Resume preparation , Soft-Skills Development.
  • 18+yrs Instructor Led Training. Flexible training to meet your needs. Semicon courses are delivered by subject matter experts and can be delivered via classroom or virtual (live on-line).
  • Self Paced Learning. Semicon offers rich self-paced training content to accelerate your learning "when you need, wherever you need". The online courses are accessible 24x7 and are organized in a way that allows you to consume the content at your own pace.
  • Synopsys and Cadence EDA Tools set for mastering best of both worlds and be Industry ready to jump-start career in VLSI.
  • Weekly Assignment Tests and 1:1s to track and make suitable adjustments to the progress of learning and mastering ASIC Verification in VLSI.

Eligibility Criteria :-

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
  • 60% through out Academics

Course Duration :-

  • 3-4 Months

Introduction to VLSI


  • Application of VLSI
  • Design Process of VLSI
  • Scope of VLSI
  • Introduction to VLSI Design flow

Digital System Design


  • Number Systems - Review
  • Logic Minimization
  • Combinational Circuit Design
  • Understanding of a Logic Gate
  • Designing with Mux, Demux, Decoders, Encoders
  • Sequential Elements - D Latch, D Flop
  • Design of Sequential Systems - Registers and Counters
  • Finite State Machine

Introduction to HDL


  • History of HDL
  • Need and Scope Of HDL

    • Basic Concepts


    • Types of Modeling
    • Data Types in Verilog, System Task
    • Logic Values
    • Port Definition, Declaration
    • Port Connection Rule

      • Gate Level Modeling


      • Gate Types
      • Gate Delays
      • Vectors in Verilog
      • Test Bench Basics
      • Writing Verilog Modules
      • Gate Level Modeling Examples

        • Dataflow Modeling


        • Type of Operators
        • Continuous assignment statement
        • Regular assignment delay
        • Examples Of Data Flow Modeling

          • Behavioral Modeling


          • Initial and Always Statements
          • Procedural Assignment Statements
          • Timing Control Statements
          • If_ else Statements
          • Case statement
          • Block Statements
          • Loops
          • Design of Flip-flops
          • Design of Digital circuits using Behavioral Modeling

            • Tasks and Functions


            State Machines


            • Moore Machines
            • Mealy Machines
            • Examples of Moore and Mealy Machines

System Verilog Overview


  • Overview of SystemVerilog
  • SystemVerilog Books and Resources

    • Data Types


    • System verilog data types and enumerated types
    • Operators
    • Queues and Arrays
    • Typedefs
    • Structures and unions
    • Casting
    • Packages
    • Strings

      • Flow Control


      • Loop enhancements
      • Tasks and Functions
      • Time values

        • OOP in System Verilog


        • Basics of OOP
        • Class Based Randomization
        • Advanced OOP
        • Class extension & inheritance
        • Adding properties & methods to extended classes
        • Overriding class methods
        • Extending class methods
        • Virtual Classes, Methods and Polymorphism
        • Dynamic Casting and Parameterized Classes
        • Callbacks

          • Advanced Concepts


          • Event scheduling in Verilog 2001
          • Event scheduling in System Verilog

            • Interfaces


            • Interface usage overview
            • How interfaces work
            • Interface constructs
            • Interface mod ports

              • Process Synchronization


              • Fork-join processes
              • Semaphores
              • Events
              • Mailboxes

                • Program Blocks


                • Program blocks
                • Program block interaction with modules
                • Final blocks
                • Clocking blocks
                • Clocking skews

                  • Functional Coverage


                  • Types of coverage
                  • Functional coverage process
                  • Cover groups and cover points
                  • Coverage bins
                  • Cross coverage

                    • System Verilog Assertion


                    • Assertion based verification
                    • Assertion types
                    • Operators
                    • Property
                    • Sequence
                    • Operations
                    • Binding SVA to Design Blocks
                    • Assertion directives

Universal Verification Methodology


  • Indroduction to UVM
  • Difference between OVM and UVM
  • Coverage-Driven Verification
  • Universal Verification Component (UVC) Structure
  • Transaction level modelling
  • UVM class library
  • UVM features

    • Stimulus Modeling


    • Modeling Transactions
    • Field Automation
    • Data Operations (copy, clone, print etc)

      • UVM Simulation Phases


      • Standard Phases
      • Run-time Phases

        • Creating a Simple Environment


        • UVM Component Classes
        • Structure of a Simple Environment
        • Driver, sequencer, monitor, agent and env
        • Messaging

          • Test Classes


          • uvm_test class
          • Test Selection

            • Configurations


            • Controlling Environment Behavior
            • Configuring Topology with set_config
            • set_config rules
            • Configuration database
            • Recommendations for set_config and uvm_config_db usage
            • Factories and Creating Data and Objects
            • Type and Instance Overrides

              • UVM Sequences


              • Sequence Components
              • uvm_do
              • Alternatives to uvm_do macros
              • Objection mechanism for stopping simulation
              • Sequence libraries

                • Configurations


                • The Testbench layer
                • Virtual SystemVerilog Interfaces
                • Assigning Interfaces using the configuration database

                  • Multi-Channel Sequences and Scoreboards


                  • Interface and Module UVCs
                  • Multi-Channel Sequences (Virtual Sequences)
                  • Building a Scoreboard

                    • Transaction Level Modeling (TLM)


                    • Concepts and Terminology
                    • Simple uni-directional interfaces (put, get, peek)
                    • More complex connections (transport, analysis)
                    • TLM FIFOs and analysis FIFOs
                    • Hierarchical connections with export
                    • Analysis

                      • Register Layer


                      • Register layer architecture and features
                      • Front door and back door access
                      • Mirroring and updating
                      • Address maps
                      • Register adapters
                      • Integrating registers into the environment
                      • Register sequences
                      • Built-in register test sequences