Physical Design Course

Course Highlights :-

  • More than 1000+ Mock interview questions and answers to equip students for cracking any job interviews , along with Cover-letter and Resume preparation , Soft-Skills Development.
  • 18+yrs Instructor Led Training. Flexible training to meet your needs. Semicon courses are delivered by subject matter experts and can be delivered via classroom or virtual (live on-line).
  • Self Paced Learning. Semicon offers rich self-paced training content to accelerate your learning "when you need, wherever you need". The online courses are accessible 24x7 and are organized in a way that allows you to consume the content at your own pace.
  • Synopsys and Cadence EDA Tools set for mastering best of both worlds and be Industry ready to jump-start career in VLSI.
  • Weekly Assignment Tests and 1:1s to track and make suitable adjustments to the progress of learning and mastering PD in VLSI.

Eligibility Criteria :-

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
  • 60% through out Academics

Course Duration :-

  • 3-4 Months

EDA Tools :-

    Tools : (Synopsys Tools)
  • Design Compiler ( For Logical and Physical Aware Synthesis )
  • IC-Compiler-2 ( For Physical Design (PD) )
  • Fusion-Compiler ( For Physical Design (PD) )
  • Star-RC ( For RC Parasitic Extraction )
  • PrimeTime ( For STA and ECOs )
  • Formality ( For LEC )
  • ICV ( For Physical Verification (DRC/LVS/ANT) )
    • Tools : (Cadence Tools)
  • Innovus ( For Physical Design (PD) )

Syllabus : ( PD – Mentorship )

  • Module 1: VLSI ( Very Large Scale Integration ) , Semiconductors , Transistors
  • Module 2: History of VLSI ( SSI/MSI/LSI )
  • Module 3: ASIC/SoC/FPGA , PPA ( Power Performance Area )
  • Module 4: Moore’s Law

  • Module 5: Combination Circuits ( AND/OR/NAND/NOR etc )
  • Module 6: Sequential Circuits ( Flip-Flops/Latches/Memorys etc )

  • Module 7: CMOS ( Complimentary Metal Oxide Semiconductor )
  • Module 8: FinFet ( Field Effect Transistors ) , Double-Patterning
  • Module 9: Technology Nodes ( 3nm/5nm/7nm/10nm/12nm/16nm etc )
  • Module 10: Fabrication Process ( Oxidation/Deposition/Lithography/ Etching/Diffusion/Ion Implantation )

  • Module 11: ASIC Cycle Flow Chart
  • Module 12: Front-End and Back-End
  • Module 13: Fab and Packaging

  • Module 14: RTL Lint and Clean-up
  • Module 15: Logic Aware Synthesis
  • Module 16: Physical Aware Synthesis
  • Module 17: Floorplan Modifications if any in Physical Aware Synthesis.
  • Module 18: DFT ( Design For Testability ) Scan Chain Insertion and Stitching , ATPG.
  • Module 19: SDC ( Synopsys Design Constraints ) Deep-Dive

  • Module 20: Init Design ( Inputs reading , Sanity Checks , ZWLM/ZIC Pre-Layout STA )
  • Module 21: Floorplan (Die Size , Macros-Placement , IOs placement , Global Congestion) , Power-Mesh ( Power Network considering EMIR ).
  • Module 22: Placement (Pre-placed cells – WellTaps/EndCaps , Coarse and Legalized std cells placement , Local Congestion , HFNS , DRVs , Setup Timing Checks in Ideal Clock , Scan Chain Re-Ordering )
  • Module 23: CTS ( Clock Tree Synthesis – Clock Tree Spec and exceptions covering NDRs , DRVs , Skew , Latency , CCD , MSCTS , Setup and Hold Timing Checks using Propagated clocks , Clock Net Routing)
  • Module 24: Routing ( Global/Track/Detail Routing , DRCs , LVS , ANT fixes , Setup and Hold Timing checks)
  • Module 25: Chip Finishing ( DFM based Metal Fill / Filler-cells )
  • Module 26: Export ( GDSII/OASIS/LEF/DEF/.lib/SDF/SPEF/NDM )

    - Physical Verification (DRC/LVS/ANT).
  • Module 27: Physical Verification DRC ( Design Rule Check )
  • Module 28: Physical Verification LVS ( Layout Versus Schematic )
  • Module 29: Physical Verification ANT (Antenna)
    • - STA and ECOs.
  • Module 30: STA ( Static Timing Analysis ) and DMSA
  • Module 31: ECOs ( Engineering Change Order )
    • - LEC/Formal-Verification.
  • Module 32: LEC ( Logical Equivalence Check )
    • - EMIR.
  • Module 33: Static EMIR
  • Module 34: Dynamic EMIR
    • - UPF and CPF Low Power Intent and checks.
  • Module 35: UPF ( Unified Power Format )
  • Module 36: CPF (Common Power Format)
  • Module 37: Static Low Power Checks for UPF and CPF

  • Module 38: TCL Scripting
  • Module 39: Perl Scripting
  • Module 40: Python Scripting
  • Module 41: Shell Scripting
  • Module 42: Unix and GVIM

  • Module 43: Mock Interviews
  • Module 44: Cover-letter and Resume Preparation
  • Module 45: Interview Guidance
  • Module 46: Soft-Skills Training

  • Module 47: ORCA_TOP using Synopsys Tools
  • Module 48: DTMF_TOP using Cadence Tools
  • Module 49: Flow Automation , AI and ML
  • Module 50: Run Time Reduction
The PD Course content is designed to cover Synthesis and Partial DFT wrt Scan ; and 5 different Sign-off checks , with Physical Design (PD) in the center. This will extensively help to open-up wide VLSI job opportunities for students as their domains expertize will be vast.


At the end of the PD Course :
  • Be experienced to handle Chip and Block level designs for both RTL to GDSII and Netlist to GDSII.
  • Gain Hands-On experience in using both Synopsys and Cadence EDA Tools.
  • Have through understanding of full ASIC/SoC Implementation flow steps.
    • Geared-up in below different Domains :
    • - Synthesis
    • - DFT for Scan Insertion and Stitching
    • - Physical Design (PD) Deep-Dive for handling Chip and Blocks.
    • - Sign-off checks wrt :
    • - Physical Verification (DRC/LVS/ANT)
    • - STA and ECOs
    • - EMIR
    • - LEC/Formal Verification
    • - UPF and CPF Low Power Intent
  • Flow automation using Scripting : Tcl/Perl/Python/Shell/Unix and GVIM.
  • Equipped with 1000+ Mock Interview Questions and Answers ,Cover-letter and Resume, Soft-Skills.