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Physical Design Corporate

Physical Design Course

Course Highlights :-

  • More than 1000+ Mock interview questions and answers to equip students for cracking any job interviews , along with Cover-letter and Resume preparation , Soft-Skills Development.
  • 18+yrs Instructor Team Led Training. Flexible training to meet your needs. Semicon courses are delivered by subject matter experts and can be delivered via classroom or virtual (live on-line).
  • Rich Learning Content. Semicon offers rich training content to accelerate your learning.
  • Synopsys or Cadence EDA Tools set for mastering tools and be Industry ready to jump-start career in VLSI.
  • Weekly Assignment Tests to track and make suitable adjustments to the progress of learning and mastering PD in VLSI.
  • Every week-end Sunday free youtube live session on Technical topics presentations.

Eligibility Criteria :-

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
  • 60% through out Academics

Course Duration :-

  • 4 Months

EDA Tools :-

  • *Design Compiler or Genus ( For Logical and Physical Aware Synthesis )
  • IC-Compiler-2 or Fusion-Compiler or Innovus ( For Physical Design (PD) )
  • *Star-RC ( For RC Parasitic Extraction )
  • *PrimeTime ( For STA and ECOs )
  • *ICV ( For Physical Verification (DRC/LVS/ANT) )

Note:-

  • Star marked tools are additional tools where overview is provided for students to have exposure. Main focus will be on PD Tools.

Working Hours :-

  • Monday to Friday (9AM to 6:30PM) and Saturday (9AM to 5PM)

Note:-

  • Institute will remain closed on sundays and all public holidays.
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Syllabus : ( PD – Mentorship )

1.Introduction to VLSI covering Moore’s law/SSI,MSI,LSI/ASIC,SoC,FPGA.
  • Module 1: VLSI ( Very Large Scale Integration ) , Semiconductors , Transistors
  • Module 2: History of VLSI ( SSI/MSI/LSI )
  • Module 3: ASIC/SoC/FPGA , PPA ( Power Performance Area )
  • Module 4: Moore’s Law
  • Duration: Week 1
2. Digital Design covering combinational and sequential circuits.
  • Module 5: Overview of Combination Circuits ( AND/OR/NAND/NOR etc )
  • Module 6: Overview of Sequential Circuits ( Flip-Flops/Latches/Memorys etc )
  • Duration: Week 1
3. CMOS,FinFet Transistors along with Fabrication process.
  • Module 7: Overview of CMOS ( Complimentary Metal Oxide Semiconductor )
  • Module 8: Overview of FinFet ( Field Effect Transistors ) , Double-Patterning
  • Module 9: Overview of Technology Nodes ( 3nm/5nm/7nm/10nm/12nm/16nm etc )
  • Module 10: Overview of Fabrication Process ( Oxidation/Deposition/Lithography/ Etching/Diffusion/Ion Implantation )
  • Duration: Week 2
4. ASIC Flow Chart.
  • Module 11: Overview of ASIC Cycle Flow Chart
  • Module 12: Overview of Front-End and Back-End
  • Module 13: Overview of Fab and Packaging
  • Duration: Week 2
5. Synthesis and DFT (Scan insertion and Stitching).
  • Module 14: Overview of RTL Lint and Clean-up
  • Module 15: Overview of Logic Aware Synthesis
  • Module 16: Overview of Physical Aware Synthesis
  • Module 17: Overview of Floorplan Modifications if any in Physical Aware Synthesis.
  • Module 18: Overview of DFT ( Design For Testability ) Scan Chain Insertion and Stitching , ATPG.
  • Module 19: Overview of SDC ( Synopsys Design Constraints ) Deep-Dive
  • Duration: Week 3-4
6. Physical Design (PD) Deep-Dive covering Floorplan/Power-Mesh/Placement/CTS/Routing/Chip-Finishing/Export.
  • Module 20: Init Design ( Inputs reading , Sanity Checks , ZWLM/ZIC Pre-Layout STA )
  • Module 21: Floorplan (Die Size , Macros-Placement , IOs placement , Global Congestion) , Power-Mesh ( Power Network considering EMIR ).
  • Module 22: Placement (Pre-placed cells – WellTaps/EndCaps , Coarse and Legalized std cells placement , Local Congestion , HFNS , DRVs , Setup Timing Checks in Ideal Clock , Scan Chain Re-Ordering )
  • Module 23: CTS ( Clock Tree Synthesis – Clock Tree Spec and exceptions covering NDRs , DRVs , Skew , Latency , CCD , MSCTS , Setup and Hold Timing Checks using Propagated clocks , Clock Net Routing)
  • Module 24: Routing ( Global/Track/Detail Routing , DRCs , LVS , ANT fixes , Setup and Hold Timing checks)
  • Module 25: Chip Finishing ( DFM based Metal Fill / Filler-cells )
  • Module 26: Export ( GDSII/OASIS/LEF/DEF/.lib/SDF/SPEF/NDM )
  • Duration: Week 5-12
7. Sign-off checks and Fixes.

Physical Verification (DRC/LVS/ANT).

    • Module 27: Overview of Physical Verification DRC ( Design Rule Check )
    • Module 28: Overview of Physical Verification LVS ( Layout Versus Schematic )
    • Module 29: Overview of Physical Verification ANT (Antenna)

– STA and ECOs.

    • Module 30: Overview of STA ( Static Timing Analysis ) and DMSA
    • Module 31: Overview of ECOs ( Engineering Change Order )

– LEC/Formal-Verification.

    • Module 32: Overview of LEC ( Logical Equivalence Check )

– EMIR.

    • Module 33: Overview of Static EMIR
    • Module 34: Overview of Dynamic EMIR

– UPF and CPF Low Power Intent and checks.

  • Module 35: Overview of UPF ( Unified Power Format )
  • Module 36: Overview of CPF (Common Power Format)
  • Module 37: Overview of Static Low Power Checks for UPF and CPF
  • Duration: Week 13-14
8. Scripting : Unix and GVIM.
  • Module 38: Overview of Scripting, Unix and GVIM
  • Duration: Week 15
9. 1000+ Mock Interview Questions and Answers , Cover-letter and Resume Preparation , Soft-Skills.
  • Module 39: Mock Interviews
  • Module 40: Cover-letter and Resume Preparation
  • Module 41: Interview Guidance
  • Module 42: Soft-Skills Training
  • Duration: Week 16
10. Practical Lab work using Synopsys or Cadence EDA Tools.
  • Module 43: ORCA_TOP using Synopsys Tools or DTMF_TOP using Cadence Tools
  • Module 44: Overview of Flow Automation
  • Module 45: Overview of AI and ML
  • Module 46: Overview of Run Time Reduction
  • Duration: Week 16

The PD Course content is designed to cover PD deep dive along with overview of Synthesis, Partial DFT wrt Scan, and 5 different Sign-off checks. This will extensively help to open-up wide VLSI job opportunities for students as their domains expertise will be vast.

  • Be experienced to handle designs for both RTL to GDSII and Netlist to GDSII.
  • Gain Hands-On experience in using EDA Tools.
  • Have through understanding of full ASIC/SoC Implementation flow steps.
  • Geared-up in below different Domains :
  • Overview of Synthesis
  • Overview of DFT for Scan Insertion and Stitching
  • Physical Design (PD) Deep-Dive for handling Chip and Blocks.
  • Overview of Sign-off checks wrt :
  • Physical Verification (DRC/LVS/ANT)
  • STA and ECOs
  • EMIR
  • LEC/Formal Verification
  • UPF and CPF Low Power Intent
  • Flow automation overview using Scripting : Tcl/Perl/Python/Shell/Unix and GVIM.
  • Equipped with 1000+ Mock Interview Questions and Answers ,Cover-letter and Resume, Soft-Skills.

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