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Design For Test Corporate

Design For Test Courses

Course Highlights :-

  • More than 500+ Mock interview questions and answers to equip students for cracking any job interviews , along with Cover-letter and Resume preparation , Soft-Skills Development.
  • 18+yrs Instructor Led Training. Flexible training to meet your needs. Semicon courses are delivered by subject matter experts and can be delivered via classroom or virtual (live on-line).
  • Self Paced Learning. Semicon offers rich self-paced training content to accelerate your learning "when you need, wherever you need". The online courses are accessible 24x7 and are organized in a way that allows you to consume the content at your own pace.
  • Cadence & Siemens EDA Tools set for mastering best of both worlds and be Industry ready to jump-start career in VLSI.
  • Weekly Assignment Tests and 1:1s to track and make suitable adjustments to the progress of learning and mastering DFT in VLSI.

Eligibility Criteria :-

  • B.E/B.Tech in ECE/EEE.
  • M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
  • 60% through out Academics

Course Duration :-

  • 16 Weeks
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MODULE - 1
  • Introduction to Design for Test (DFT)
  • Overview of SOC flow for DFT
  • Digital Circuits related to DFT
  • Sample Verilog Syntax
  • Duration: 1 Week
MODULE - 2
    • IEEE 1149.1 JTAG Architecture and Operation
    • TAP Controller and FSM
    • JTAG and Boundary Scan
    • BSR Cell Types and Usage
    • IEEE 1687 iJTAG Architecture
    • ICL, PDL Overview
  • Labs
  • Duration: 2 Weeks
MODULE - 3
  • SCAN Architecture Overview
  • Types of SCAN cells
  • Scan Chains Operation
  • Various DFT Blocks (for SCAN)
  • Duration: 1 Week
MODULE - 4
  • Block level SCAN Insertion Flow (Without Compression)
  • Multiple Clock Handling
  • Analysis of various SCAN DRC’s
  • DRC Fixes with Examples
  • How to handle Pre-existing chain (like CTL)
  • Labs
  • Duration: 2 Weeks
MODULE - 5
  • Needs of Compression Logic
  • Compression Architecture
  • Different Compression Techniques
  • SCAN Stitching with Compression
  • Block level SCAN Insertion Flow (with Compression)
  • Different types of Mask techniques
  • LEC Checks (Pre vs Post Scan Insertion)
  • Labs
  • Duration: 2 Weeks
MODULE - 6

Introduction to ATPG
Understanding of Defects and Faults
Types of Fault models
Block level ATPG Flow (Stuck-At)
ATPG constraints and Analysis
ATPG DRC analysis (C, D, K, and T rules)

Test Coverage Analysis

Coverage Improvement Techniques

Labs
Duration: 2 Weeks

MODULE - 7
  • Different Types of At-Speed Fault Models
  • At-Speed fault model (In Details)
  • Concept of LOC, LOS and LEOS
  • On-Chip clocking for At-Speed Testing
  • ATPG TDF Setup and Pattern Generation
  • Analysing Low TDF coverage and Improvement
  • ATPG TDF Setup and Pattern Generation
  • Introduction to Test Point Insertion
  • Labs
  • Duration: 2 Weeks
MODULE - 8
  • Introduction to Static Timing Analysis
  • Different Timing Corners
  • Timing Constraints (Test Modes)
  • Sample SDC file (Test Modes)
  • Duration: 1 Week
MODULE - 9
  • Simulation Overview (Zero-delay, Unit-delay)
  • Different between Parallel and Serial simulations
  • Pattern Simulation and Debug (Chain, Logic, Parallel, Serial)
  • Timing Simulations with SDF
  • Labs
  • Duration: 1 Week
MODULE - 10
  • Introduction to MBIST
  • MBIST Architecture Overview and Memory Grouping
  • Memory Fault types and Memory Testing Algorithms
  • MBIST Insertion Flow (Bottom-Up)
  • MBIST Pattern Generation Flow
  • MBIST Pattern Verification
  • Labs
  • Duration: 2 Weeks

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