Advanced Physical Design
- Die Size optimization techniques
- Floor-planning rules as per lower technology rules
- Group Paths, weights, Magnet placement, Bounds, CCD in Placement
- Custom Balance points in CTS for timing closure
- Clock gating cloning and de-cloning
- Overview of different sign-off checks which includes Physical Verification, PT-STA, ECO’s, LEC, RedHawk EMIR, Low Power checks of UPF and CPF
Semicon Technolabs
Ranked as one of the 10 most promising Semiconductor Companies – 2019 by Silicon India